1. Field of the Invention
The present disclosure relates to an electronic signal amplifier. It also relates to an article for determining the gain of such an amplifier.
2. Description of the Related Art
An amplifier corresponding to the circuit diagram in FIG. 1 is known to those skilled in the art. Such an amplifier comprises a given number N of quadrupolar amplification cells referenced C1, C2, . . . , CN connected in series, where N is an integer greater than or equal to unity. By reason of this structure, the amplifier is classed as a “distributed amplifier”. It additionally comprises a power source 10 having a ground node or terminal 3 and a positive supply node or terminal 4.
The cell C1 comprises a capacitor 11 of capacitance Γ1, a transistor 12, for example of the n-MOS type, and two inductors 13 and 14 of respective values L13 and L14. The source of the transistor 12 is connected to the terminal 3, and the drain of the transistor 12 is connected to the terminal 4 via the capacitor 11. The gate of the transistor 12 is connected to a first output of the cell C1 and is connected to a first input of the cell C1 via the inductor 13. The drain of the transistor 12 is connected to a second input of the cell C1 via the inductor 14 and is connected to a second output of the cell C1.
All the amplification cells have structures identical to that of the cell C1. Thus, the cell Cn comprises a capacitor n1 of capacitance Γn, a transistor n2 and two inductors n3 and n4 of respective values Ln3 and Ln4, n being an integer between 1 and N. The capacitors 11, 21, . . . , N1 may be identical to each other, as may the transistors 12, 22, . . . , N2. Each transistor 12, 22, . . . , N2 has an internal capacitance Γe1, Γe2, . . . , ΓeN between the gate and the source of this transistor. The inductors 13, 23, . . . , N3 may also be identical to each other, as may the inductors 14, 24, . . . , N4.
The amplification cell Cn, for n in the range 2 to N−1 (n=2, . . . , N−1), is connected in the following manner to the cells Cn−1 and Cn+1: the first and second inputs of the cell Cn are connected to the first and second outputs of the cell Cn−1, respectively, and the first and second outputs of the cell Cn are connected to the first and second inputs of the cell Cn+1, respectively.
The first input of the cell C1 forms an input 1i of the amplifier: it receives an input electronic signal “IN”. The second input of the cell C1 is connected to the terminal 3 via a resistor 5. The first output of the last cell CN is connected to the terminal 3 via an inductor referenced (N+1)3 in series with a 6. Finally, the second output of the cell CN is connected to an output 2o of the amplifier via an inductor (N+1)4. It delivers the amplified signal which forms the amplifier output signal “OUT”.
In addition, the input of the amplifier is positively biased in a known fashion.
The voltage gain Av of such an amplifier can be calculated in the following manner.
A first imaginary delay line is initially defined that is formed by the inductors 13, 23, . . . N3, (N+1)3 connected in series one after the other, and by the capacitors associated with the internal capacitances of the transistors 12, 22, . . . , N2, connected, at one end, to nodes between the inductors 13, 23, . . . , N3, (N+1)3 and, at the other end, to the terminal 3. This first delay line is called the input delay line of the amplifier. The attenuation introduced by the input delay line is denoted Ae, and a characteristic impedance Ze of the input delay line is given by the equation:
                              Z          e                =                                                            ∑                                  n                  =                  1                                N                            ⁢                              L                n3                                                                    ∑                                  n                  =                  1                                N                            ⁢                              Γ                en                                                                        (        1        )            
In the same way, a second imaginary delay line, referred to as the output delay line of the amplifier, is defined. The output delay line comprises the inductors 14, 24, . . . , N4, (N+1)4, connected in series one after the other, and the capacitors 11, 21, . . . , N1, connected, at one end, to nodes between the inductors 14, 24, . . . , N4, (N+1)4 and, at the other end, to the terminal 4. The attenuation introduced by the output delay line is denoted As, and a characteristic impedance Zs of the output delay line is given by the equation:
                              Z          s                =                                                            ∑                                  n                  =                  1                                N                            ⁢                              L                n4                                                                    ∑                                  n                  =                  1                                N                            ⁢                              Γ                n                                                                        (        2        )            
The voltage gain Av of the amplifier is then given by the equation:
                              A          v                =                              g            m            2                    ×                                                    Z                e                            ⁢                              exp                ⁡                                  (                                      -                                          NA                      e                                                        )                                            ⁢                              ×                s                            ⁢                              exp                (                                  -                                      NA                                          s                      ⁢                                                                                          )                                                                                                          4              ⁢                                                (                                                            A                      e                                        -                                          A                      s                                                        )                                2                                                                        (        3        )            where gm denotes the transfer coefficient of the transistors 12, 22, . . . , N2 at the biasing point of the latter. In other words, gm is the ratio of a variation in the current flowing between the drain and the source of each transistor 12, 22, . . . , N2 to a variation in the electrical potential on the gate of this transistor.
An amplifier according to FIG. 1 has a low electrical power consumption since it comprises neither feedback loops nor resistors between the terminals 3 and 4. Moreover, it exhibits a very wide bandwidth, compatible with a high data rate content in the amplified signal. This rate can reach 10 GHz. For this reason, such an amplifier is commonly referred to as a UWB (Ultra Wide Band) amplifier.
Such a UWB amplifier comprises 2×(N+1) inductors. In order to obtain an amplifier with a high output current capability, there must be a sufficiently large number of amplification cells N. Usually, N is equal to at least 3, implying that the amplifier comprises at least 8 inductors which leads to a high cost of production for the amplifier.